In the development of semiconductor memory technology the cost of developing new technology has lead to the practice that each succeeding generation of memory products contains four times the number of memory bits as the proceding generation. For example, the sequence of Dynamic RAM (DRAM) products has followed the geometrical series of 1-Megabit (Mb), 4 Mb, 16 Mb and 64 Mb. (A megabit corresponds to 2.sup.20 or 1,048,576 bits.)
Each generation strives to provide similar functions and organizational features as found in previous generations; however, the compatibility of addressing schemes has dictated that each suceeding generation of Random Access Memory (RAM) utilize additional address input signals to address the increasing number of memory cells found in each suceeding generation of memory devices. The additional address input signals act to increase the memory depth of the DRAM memory device. Because the increase in depth or total addressable memory has out-stripped the utilization of memory at the system level, the historical tradition of providing only a single bit per DRAM chip has been altered to provide different granularity of data bits. For example, a 16 Mb DRAM may be offered in organizations of 16 MbX1, 4 MbX4, 2 MbX8, or even 1 MbX16.(The "Xn" portion of such designation is recited as "by n", such as "by 1.") A X4 chip can be used to replace four X1 chips of the previous generation. These wider I/O chips enable later generations of technology to functionally replace earlier generations without requiring a completely new addressing scheme to be designed.
In fabrication semiconductor memory devices it is a common practice to package a plurality of DRAM chips on a single assembly or sub-assembly called a single in-line package (SIP) or a single in-line memory module (SIMM) in which the memory components are organized to provide accessed memory data to a host processor or system in units known as bytes. Each data byte typically contains eight data bits, where each of the bits is supplied by one output of the plurality of DRAM chips comprising the memory system. The number of bytes which the memory system provides to the host processor, like the granularity of DRAMs, has typically been based on powers of 2. Previous generations of processors have used memory systems that provide two concurrent bytes of information, while present generations of processors typically use memory systems that can provide 4 or 8 concurrent bytes of data. In order to keep the number of memory chips used in the memory system from growing proportionally to the number of concurrent bytes provided, wider I/O DRAM chips are used. Hence, in the 1 Mb memory generation, memory systems were typically built with X1 chips while in the 4 Mb memory generation, memory systems are typically built with X4 memory chips. The organization of SIPs or SIMMs with these wider I/O memory chips has been rather uncomplicated.
In high reliability systems it is preferred to utilize some sort of error detection with or with out error correction in conjunction with memory systems. The simplest way to implement error detection is to add a single "parity" bit to each byte which is a function of all of the bits in a byte. At present, it is common to add a ninth parity bit to eight-bit bytes. The additional bits require a memory system which can accommodate a nine bit byte organizations. This requirement has been met in the past by building the memory system out of multiples of nine X1 chips. However, as stated above, for the memory generations beyond the 1Mb generation, using X1 memory chips causes the total memory contained in the memory system to exceed the amount that can be practically used. Furthermore, a common feature of DRAM memory system organizations is that each nine bit byte can be independently accessible. Thus, even for memory systems which can concurrently provide 4 or 8 bytes of data, each byte must be addressable.
A solution to this granularity problem has been proposed by Neal and Poteet in their U.S. Pat. No. 5,089,993 where they describe two approaches to the above problem. In designing a SIP or SIMM organized as 256K bytes X 36 bits (four 9-bit words), they describe using eight 1 Mb DRAMs organized as 256KX4 and four 256 Kb organized as 256 KbX1 requiring a total of twelve memory chips. A problem associated with this approach is that memory processing and development technology rarely allow the manufacture of different density chips in the same technology. Because memory development trends not only demand a four-fold increase in chip density for each subsequent generation of product but also demand an increase in performance, that is, decreased access time, etc. Thus, it would be rare, indeed, to find a 1 Mb DRAM having the same performance as its 256 Kb predecessor. The proposed combination would be practical only if the 1 Mb DRAMs were operated at the slower rate dictated by the 256 Kb DRAM.
The solution, put forward by Neal and Poteet, uses a plurality of chips all of a common generation of technology, but requires two different memory chip architectures. A new chip design which has the density of 1 Mb is organized as four separate 256 KbX1 memories and is designated as Quad CAS. Each of the four memories on a chip is responsive to a different column address strobe (CAS) input (CAS1...CAS4) and each CASn selects one of four data input/output ports. The solution they describe is intended to work for a memory system which is comprised of a plurality of X4 chips. Extending this solution to a memory system which is comprised of a plurality of X8 (wider I/O) memory chips would require a corresponding increase in the number of seperate CAS inputs for the designated "Quad CAS" chip. Hence, using a plurality of X8 chips would seem to require an eight-way CAS chip.
In each of the above approaches to solving the problem of dealing with a byte size that is not an integer power of two, the solution uses one or more dedicated chips solely to provide the odd ninth data bit.